The manufacturing of integrated circuits aims for continuously decreasing feature sizes of the fabricated components. For certain components, like capacitors, shrinking adversely affects the properties of the component. In order to achieve a minimum value of capacitance, it is therefore necessary to maintain the surface area of the capacitor above a threshold value. This is in particular important for dynamic random access memory cells (DRAM) which call for high integration densities.
As the surface area for a single memory cell decreases, the capacity of the storage capacitor is decreasing as well. For proper operation of the memory cell, a certain minimum capacity (typically in the order of 30 femto farad) is mandatory for the storage capacitor. If the capacity of the storage capacitor is too small, the charge stored in the storage capacitor is not sufficient to produce a detectable signal. In such a case, the information stored in the memory cell is lost and the memory cell is not operating in the desired way.
Several concepts have been developed to overcome the problems associated with shrinking feature sizes by integrating capacitors of DRAM cells in a three dimensional way.
A first example introduces deep trench capacitors which are formed in the substrate of a semiconductor wafer to maintain a large capacitor area with a high capacity while using only a small amount of the surface of the substrate. The selection or access transistor is usually formed on the planar surface of the substrate.
In another example, stacked capacitors are used which are formed on top of a planar surface on the substrate. The selection transistors are formed below the planar surface. The stacked capacitor comprises a first electrode and a second electrode having a dielectric layer in-between. The first electrode (also called bottom electrode) is usually formed as a cylindrical structure on the surface of the substrate by lining trenches of a patterned sacrificial mold layer with the electrode material. Afterwards, the bottom electrodes are released by etching the sacrificial layer. Subsequently, the surface of the, e.g. cylindrical shaped, bottom electrodes are cleaned to be prepared for further processing including disposing the dielectric layer and the second or top electrode.
However, with decreasing feature sizes of structures, etching and/or cleaning steps become increasingly difficult. Etching and/or cleaning are usually performed by wet processing. Standard wet processing, e.g. rinsing the wafer with ultra pure deionized water for cleaning purposes, introduces capillary forces between neighboring structures, i.e. between adjacent bottom electrodes. With reduced feature sizes, this may lead to adhesion of neighboring structures mediated by the cleaning liquid, usually referred to as “stiction”. Stiction is primarily important during drying steps which usually follow the etching and cleaning steps in semiconductor wafer processing. There, capillary forces induced by the liquid lead to adhesion of adjacent bottom electrodes. The adjacent bottom electrodes remain stuck to each other even after being completely dried, if the adhesion force between the contacting adjacent bottom electrodes is larger than the elastic restoring force of the deformed bottom electrodes.
Additionally, exposing wafers to an air-liquid interface during transfer between etching, cleaning and drying process modules is one of the potential issues to be overcome in order to obtain stiction free process performance.
Failing to achieve stiction free process performance would ultimately result in a low yield of the produced circuits. One potential solution would be to completely avoid wet processing and perform etching steps using gas phase processing, e.g. in a hydrogen fluoride vapor. Disadvantageously, this processing leads to etching residues and to silicon surface termination states which hinders further processing.